{"product_id":"intel-max®-10-fpga-part-10m02scu169a7g-fpga-dex","title":"Intel MAX 10 FPGA, Part #10M02SCU169A7G | FPGA | DEX","description":"\u003cp\u003eIntel MAX 10 FPGA, Part #10M02SCU169A7G | FPGA | DEX\u003c\/p\u003e\n\u003cp\u003eFeatures\u003c\/p\u003e\n\u003cul\u003e\n\u003cli\u003eVIN range: 0 V ≤ VIN ≤ 1.85 V. \u003c\/li\u003e\n\u003cli\u003eRL range: 90 ≤ RL ≤ 110 Ω. \u003c\/li\u003e\n\u003cli\u003eLow VOD setting is only supported for RSDS standard. \u003c\/li\u003e\n\u003cli\u003eNo fixed VIN , VOD , and VOS specifications for Bus LVDS (BLVDS).\u003c\/li\u003e\n\u003cli\u003eThey are dependent on the system topology. Mini-LVDS, RSDS, and Point-to-Point Differential Signaling (PPDS) standards are only supported at the output pins for Intel MAX 10 devices. \u003c\/li\u003e\n\u003cli\u003eSupported with requirement of an external level shift. Sub-LVDS input buffer is using 2.5 V differential buffer. \u003c\/li\u003e\n\u003cli\u003eDifferential output depends on the values of the external termination resistors. Differential output offset voltage depends on the values of the external termination resistors.\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003cp\u003e \u003c\/p\u003e\n\u003cp\u003eITL:10M02SCU169A7G \u003c\/p\u003e\n\u003cp\u003e10M02SCU169A7G \u003c\/p\u003e","brand":"Intel","offers":[{"title":"Default Title","offer_id":43011614245063,"sku":"ITL:10M02SCU169A7G","price":185.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0480\/2750\/0701\/products\/intel-maxr-10-fpga-part-10m02scu169a7g-fpga-dex-information-technology-intel-630633.jpg?v=1674081038","url":"https:\/\/edexdealstest.myshopify.com\/en-apac\/products\/intel-max%c2%ae-10-fpga-part-10m02scu169a7g-fpga-dex","provider":"DEX TEST","version":"1.0","type":"link"}