{"product_id":"intel-fpga-cyclone-part-ep3c5e144a7n-fpga-dex","title":"Intel FPGA Cyclone Part #EP3C5E144A7N | FPGA | DEX","description":"\u003cp\u003eCyclone III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power consumption, Cyclone III device family provides the ideal solution for your high-volume, low-power, and cost-sensitive applications. To address the unique design needs, Cyclone III device family offers the following two variants:\u003c\/p\u003e\n\u003cul\u003e\n\u003cli\u003eCyclone III—lowest power, high functionality with the lowest cost\u003c\/li\u003e\n\u003cli\u003eCyclone III LS—lowest power FPGAs with security\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003cp\u003eWith densities ranging from about 5,000 to 200,000 logic elements (LEs) and 0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power consumption, Cyclone III device family makes it easier for you to meet your power budget. Cyclone III LS devices are the first to implement a suite of security features at the silicon, software, and intellectual property (IP) level on a low-power and high-functionality FPGA platform. This suite of security features protects the IP from tampering, reverse engineering and cloning. In addition, Cyclone III LS devices support design separation which enables you to introduce redundancy in a single chip to reduce size, weight, and power of your application\u003c\/p\u003e\n\u003cp\u003eFeatures:\u003c\/p\u003e\n\u003cul\u003e\n\u003cli\u003eConfiguration security using advanced encryption standard (AES) with 256-bit volatile key\u003c\/li\u003e\n\u003cli\u003eRouting architecture optimized for design separation flow with the Quartus II software\u003c\/li\u003e\n\u003cli\u003eDesign separation flow achieves both physical and functional isolation between design partitions\u003c\/li\u003e\n\u003cli\u003eAbility to disable external JTAG port\u003c\/li\u003e\n\u003cli\u003eError Detection (ED) Cycle Indicator to core\u003c\/li\u003e\n\u003cli\u003eProvides a pass or fail indicator at every ED cycle\u003c\/li\u003e\n\u003cli\u003eProvides visibility over intentional or unintentional change of configuration random access memory (CRAM) bits\u003c\/li\u003e\n\u003cli\u003eAbility to perform zeroization to clear contents of the FPGA logic, CRAM, embedded memory, and AES key\u003c\/li\u003e\n\u003cli\u003eInternal oscillator enables system monitor and health check capabilities\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003cp\u003e \u003c\/p\u003e\n\u003cp\u003eITL:EP3C5E144A7N \u003cspan data-mce-fragment=\"1\"\u003e \u003c\/span\u003e\u003c\/p\u003e\n\u003cp\u003eEP3C5E144A7N \u003cspan\u003e \u003c\/span\u003e\u003c\/p\u003e","brand":"Intel","offers":[{"title":"Default Title","offer_id":43011530621127,"sku":"ITL:EP3C5E144A7N","price":750.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0480\/2750\/0701\/products\/intel-fpga-cyclone-part-ep3c5e144a7n-fpga-dex-information-technology-intel-463723.jpg?v=1674078307","url":"https:\/\/edexdealstest.myshopify.com\/en-amer\/products\/intel-fpga-cyclone-part-ep3c5e144a7n-fpga-dex","provider":"DEX TEST","version":"1.0","type":"link"}