{"product_id":"intel-central-processing-unit-part-cm8063401293902s-r1a4-cpu-dex","title":"Intel Central Processing Unit part #: CM8063401293902S R1A4 | CPU | DEX","description":"\u003cp\u003eIntel Central Processing Unit part #: CM8063401293902S R1A4 Processor Featuer Details:\u003c\/p\u003e\n\u003cp\u003e• Each core supports two threads (Intel® Hyper-Threading Technology), up to 16 threads per socket • 46-bit physical addressing and 48-bit virtual addressing • 1 GB large page support for server applications • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction\/data mid-level (L2) cache for each core • Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction\/data last level cache (LLC), shared among all cores\u003c\/p\u003e\n\u003cp\u003e \u003c\/p\u003e\n\u003cp\u003eSystem Memory Support\u003c\/p\u003e\n\u003cp\u003e• Intel® Xeon® processor E5-2400 product family product family supports three DDR3 channels • Unbuffered DDR3 and registered DDR3 DIMMs • LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher capacity memory subsystems • Independent channel mode or lockstep mode • Data burst length of eight cycles for all memory organization modes • Memory DDR3 data transfer rates of 800, 1066, 1333, and 1600 MT\/s • 64-bit wide channels plus 8-bits of ECC support for each channel • DDR3 standard I\/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V • 1-Gb, 2-Gb and 4-Gb DDR3 DRAM technologies supported for these devices: — UDIMMs x8, x16 — RDIMMs x4, x8 — LRDIMM x4, x8 (2-Gb and 4-Gb only) • Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM • Open with adaptive idle page close timer or closed page policy • Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC (with or without data scrambler) or a predefined test pattern • Minimum memory configuration: independent channel support with 1 DIMM populated • Integrated dual SMBus master controllers • Command launch modes of 1n\/2n • RAS Support (including and not limited to): — Rank Level Sparing and Device Tagging — Demand and Patrol Scrubbing — DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM device failure. Independent channel mode supports x4 SDDC. x8 SDDC requires lockstep mode — Lockstep mode where channels 2 \u0026amp; 3 are operated in lockstep mode — Data scrambling with address to ease detection of write errors to an incorrect address. — Error reporting via Machine Check Architecture — Read Retry during CRC error handling checks by iMC — Channel mirroring within a socket • Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT) • Memory thermal monitoring support for DIMM temperature via two memory signals, MEM_HOT_C{1\/23}_N\u003c\/p\u003e\n\u003cp\u003e \u003c\/p\u003e\n\u003cp\u003eITL:CM8063401293902S R1A4\u003c\/p\u003e\n\u003cp\u003eCM8063401293902S R1A4\u003c\/p\u003e","brand":"Intel","offers":[{"title":"Default Title","offer_id":43011750101191,"sku":"ITL:CM8063401293902S R1A4","price":1052.7,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0480\/2750\/0701\/products\/intel-central-processing-unit-part-cm8063401293902s-r1a4-cpu-dex-information-technology-intel-389082.jpg?v=1674086065","url":"https:\/\/edexdealstest.myshopify.com\/en-amer\/products\/intel-central-processing-unit-part-cm8063401293902s-r1a4-cpu-dex","provider":"DEX TEST","version":"1.0","type":"link"}